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Mapping of Match Tables from P4 Language to FPGA Technology
Kekely, Michal ; Matoušek, Jiří (referee) ; Kořenek, Jan (advisor)
This thesis deals with design and implementation of mapping of match action tables from P4 language to FPGA technology. Goal of the thesis was to describe key principles, which need to be understood in order to design such a mapping and function of algorithms needed, apply these principles by implementing them and analyze the speed and memory requirements of such an implementation. Outcome provides configurable hardware unit capable of classifying packets and connection between the unit and match action tables from P4 language. The implementation is based on DCFL algorithm and requires less memory compared to HiCuts and HyperCuts algorithms while being comparably fast at worst-case scenarios.
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Control Flow Graph for P4 Programs
Ponek, Timotej ; Šišmiš, Lukáš (referee) ; Kekely, Lukáš (advisor)
Concept of SDN gradually became one of the most popular solutions for network management. It allows rapid reconfigurability of network devices, to reflect actual demands and to enable quick testing of new solutions, which supports overall advance in networking. This thesis focuses on P4 programming language, which is one of the implementations of SDN concept. The goal of this thesis is improvement of the existing open-source P4 compiler. More precisely, extension of a part used to generate control flow graphs. New implementation captures program flow even inside match-action tables and actions, which allows easier checking of compiler output and further optimization of compiler to reduce dead code. It also provides option to generate a fullgraph in dot format and a predefined json format that captures the flow of the program across all function blocks of the P4 program.
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Control Flow Graph for P4 Programs
Ponek, Timotej ; Šišmiš, Lukáš (referee) ; Kekely, Lukáš (advisor)
Concept of SDN gradually became one of the most popular solutions for network management. It allows rapid reconfigurability of network devices, to reflect actual demands and to enable quick testing of new solutions, which supports overall advance in networking. This thesis focuses on P4 programming language, which is one of the implementations of SDN concept. The goal of this thesis is improvement of the existing open-source P4 compiler. More precisely, extension of a part used to generate control flow graphs. New implementation captures program flow even inside match-action tables and actions, which allows easier checking of compiler output and further optimization of compiler to reduce dead code. It also provides option to generate a fullgraph in dot format and a predefined json format that captures the flow of the program across all function blocks of the P4 program.
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|
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Mapping of Match Tables from P4 Language to FPGA Technology
Kekely, Michal ; Matoušek, Jiří (referee) ; Kořenek, Jan (advisor)
This thesis deals with design and implementation of mapping of match action tables from P4 language to FPGA technology. Goal of the thesis was to describe key principles, which need to be understood in order to design such a mapping and function of algorithms needed, apply these principles by implementing them and analyze the speed and memory requirements of such an implementation. Outcome provides configurable hardware unit capable of classifying packets and connection between the unit and match action tables from P4 language. The implementation is based on DCFL algorithm and requires less memory compared to HiCuts and HyperCuts algorithms while being comparably fast at worst-case scenarios.
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